Thin film diode integrated with chalcogenide memory cell

ABSTRACT

An integrated programmable conductor memory cell and diode device in an integrated circuit comprises a diode and a glass electrolyte element, the glass electrolyte element having metal ions mixed or dissolved therein and being able to selectively form a conductive pathway under the influence of an applied voltage. In one embodiment, both the diode and the memory cell comprise a chalcogenide glass, such as germanium selenide (e.g., Ge 2 Se 8  or Ge 25 Se 75 ). The first diode element comprises a chalcogenide glass layer having a first conductivity type, the second diode element comprises a chalcogenide glass layer doped with an element such as bismuth and having a second conductivity type opposite to the first conductivity type and the memory cell comprises a chalcogenide glass element with silver ions therein. In another embodiment, the diode comprises silicon and there is a diffusion barrier layer between the diode and the chalcogenide glass memory element. Methods of fabricating integrated programmable conductor memory cell and diode devices are also disclosed.

FIELD OF THE INVENTION

This invention relates generally to a method of manufacture for memorydevices in integrated circuits and more particularly to programmableconductor memory arrays comprising glass electrolyte elements.

BACKGROUND OF THE INVENTION

The digital memory most commonly used in computers and computer systemcomponents is the dynamic random access memory (DRAM), wherein voltagestored in capacitors represents digital bits of information. Electricpower must be supplied to the capacitors to maintain the informationbecause, without frequent refresh cycles, the stored charge dissipates,and the information is lost. Memories that require constant power areknown as volatile memories.

Non-volatile memories do not need frequent refresh cycles to preservetheir stored information, so they consume less power than volatilememories and can operate in an environment where the power is not alwayson. There are many applications where non-volatile memories arepreferred or required, such as in cell phones or in control systems ofautomobiles. Non-volatile memories include magnetic random accessmemories (MRAMs), erasable programmable read only memories (EPROMs) andvariations thereof.

Another type of non-volatile memory is the programmable conductor orprogrammable metallization memory cell, which is described by Kozicki etal. in (U.S. Pat. No. 5,761,115; No. 5,914,893; and No. 6,084,796) andis included by reference herein. The programmable conductor cell ofKozicki et al. (also referred to by Kozicki et al. as a “metal dendritememory”) comprises a glass ion conductor, such as a chalcogenide-metalion glass and a plurality of electrodes disposed at the surface of thefast ion conductor and spaced a distance apart from one another. Theglass/ion element shall be referred to herein as a “glass electrolyte,”or, more generally, “cell body.”

When a voltage is applied to the anode and the cathode, a non-volatileconductive pathway (considered a sidewall “dendrite” by Kozicki et al.)grows from the cathode through or along the cell body towards the anode,shorting the electrodes and allowing current flow. The dendrite stopsgrowing when the voltage is removed. The dendrite shrinks, re-dissolvingmetal ions into the cell body, when the voltage polarity is reversed. Ina binary mode, the programmable conductor cell has two states; afully-grown dendrite or shorted state that can be read as a 1, and astate wherein the dendrite does not short out the electrodes that can beread as a 0, or vice versa. It is also possible to arrange variableresistance or capacitance devices with multiple states.

The recent trends in memory arrays generally have been to form first avia, then fill it with a memory storage element (e.g., capacitor) andetch back. It is simple to isolate individual memory cells in this way.Programmable memory cells also have been fabricated using this so-calledcontainer configuration, wherein the electrodes and cell body layers aredeposited into a via that has been etched into an insulating layer.Metal diffusion in the course of growing and shrinking the conductivepathway is confined by the via wall. The memory cell can be formed in anumber of array designs. For example, in a cross-point circuit design,memory elements are formed between upper and lower conductive lines atintersections. When forming a programmable conductor array with theglass electrolyte elements similar to those of Kozicki et al., vias areformed in an insulating layer and filled with the memory cell bodies,such as metal-doped glass electrolyte or glass fast ion diffusion (GFID)elements.

Accordingly, a need exists for improved methods and structures forforming integrated programmable conductor memory arrays.

SUMMARY OF THE INVENTION

An integrated programmable conductor memory cell and diode device in anintegrated circuit is provided. The device comprises at least a firstdiode element, a glass electrolyte element over the first diode element,and a top electrode in contact with the glass electrolyte element. Theglass electrolyte element has metal ions mixed or dissolved therein andis able to selectively form a conductive pathway under the influence ofan applied voltage.

In accordance with one aspect of the present invention, a memory device,comprising an integrated diode and programmable conductor memory cell isprovided wherein both the diode and the memory cell comprise achalcogenide glass.

In one embodiment, an integrated programmable conductor memory cell anddiode device is provided. The device comprises a first polysilicon layerwith a first conductivity type doping, a layer of germanium selenideglass containing metal ions over the first polysilicon layer and a topelectrode over the layer of germaniumselenide glass. The device canfurther comprise a silicon substrate region having a second conductivitytype doping, opposite to the first conductivity type doping, wherein thesilicon substrate region is in direct contact with the first polysiliconlayer.

In accordance with another aspect of the invention, a method offabricating a PCRAM (programmable conductor random access memory) isprovided. The method comprises forming an insulating layer with an arrayof vias, providing at least one diode element in each via and providinga chalcogenide glass memory element over the diode element in each via.The chalcogenide glass memory element has metal ions therein and iscapable of selectively forming a conductive pathway under the influenceof an applied voltage.

In yet another aspect of the invention, a method for making a PCRAM cellwith an integrated thin film diode in a via is provided. The methodcomprises providing a diffusion barrier material at a bottom of the via,depositing a first chalcogenide glass to fill the via, etching the firstchalcogenide glass back to form a recess in the via, doping the firstchalcogenide glass to a predetermined depth after etching, forming amixture of a second chalcogenide glass and a first conductive materialto fill the via after doping and depositing a second conductive materialover the mixture.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects of the invention will be readily understood bythe skilled artisan in view of the detailed description of the preferredembodiments below and the appended drawings, which are meant toillustrate and not to limit the invention, and in which:

FIG. 1 is a cross section of a partially fabricated integrated circuit,showing a via in a silicon nitride layer over a bottom conducting line.

FIG. 2 shows the via of FIG. 1 after filling the via with germaniumselenide (Ge—Se) glass.

FIG. 3 shows the filled via of FIG. 2 after etching back to recess theGe—Se glass into the via.

FIG. 4 shows the Ge—Se glass in the via of FIG. 3 after ion implantingto dope a top portion of the Ge—Se layer.

FIG. 5 shows the Ge—Se layer of FIG. 4 after an additional layer ofGe—Se glass has been deposited to fill the via.

FIG. 6A shows the filled via of FIG. 5 after planarization to make theGe—Se and the surrounding silicon nitride coplanar and subsequent metaldeposition and patterning to make a top electrode, in accordance withone embodiment of the present invention.

FIG. 6B shows the structure of FIG. 6A after formation of a topconductor.

FIG. 7A shows the filled via of FIG. 5 after deposition of a metal layerover the Ge—Se glass, in accordance with another embodiment of thepresent invention.

FIG. 7B shows the structure of FIG. 7A after patterning and etching themetal layer and the Ge—Se overlayer.

FIG. 7C shows the structure of FIG. 7B after formation of a topconducting line.

FIG. 8 is a cross section showing another embodiment of the inventionwherein an integrated programmable conductor memory cell and diodedevice comprises a Ge—Se doped layer extending down to a bottomconducting line and overlaid by an undoped layer of Ge—Se glass.

FIG. 9 is a cross section showing another embodiment of the inventionwherein a diode comprises a p⁺ polysilicon layer and an n⁺ polysiliconlayer, integrated with a programmable conductor memory cell.

FIG. 10 is a cross section showing another embodiment of the inventionwherein two integrated programmable conductor memory cell and diodedevices are shown. A silicon nitride layer having two vias has beenformed directly on a silicon substrate. The diodes comprise theunderlying p⁺ region of the substrate and n⁺ polysilicon layers at thebottom of the vias.

FIG. 11 is a cross section showing an alternative arrangement of theembodiment of FIG. 10 wherein first n⁺ polysilicon layers are formed incontact with an underlying p⁺ region of the substrate, and then narrowerprogrammable conductor memory cells are formed in vias in a siliconnitride layer to land on the top surfaces of the diode structures.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A simple diode comprises two diode elements, or sides of oppositeconductivity type, in contact with each another, which form a p-njunction at their interface. More complex structures can be made frommultiple diode elements.

It is desirable to have a diode connected in series with each memorycell in an array. This allows for discrete switching of the memory cellas a certain level of forward bias is needed to overcome the diodebarrier. Above that voltage, current flows easily through the diode.This diode barrier prevents accidental switching of the memory element.It is further desirable that the diode be “leaky,” that is, that itallow a small amount of conduction when reverse biased to allow atrickle current for reading the memory cell state.

For the purpose of this disclosure, an integrated programmable conductormemory cell and diode device is defined as a device that incorporatesboth a programmable conductor memory cell and a diode so that theyfunction together, without intervening electrical devices or lines,although layers such as optional diffusion barriers (described below)can intervene. Several embodiments are discussed comprising variousconfigurations wherein a programmable conductor memory cell and diodeelements are arranged to perform this function.

The aforementioned needs are satisfied by the preferred embodiments ofthe present invention, which provide integrated programmable conductormemory cells and diode devices and methods for making the same. Theadvantages of the embodiments will become more fully apparent from thefollowing description taken in conjunction with the accompanyingdrawings.

Reference will now be made to the drawings wherein like numerals referto like parts throughout. The figures have not been drawn to scale.

A programmable conductor memory element comprises a glass electroltyteelement, such as a chalcogenide glass element with metal ions mixed ordissolved therein, which is capable of forming a conductive pathwayalong or through the glass element under the influence of an appliedvoltage. The extent of the conductive pathway depends upon appliedvoltage and time; the higher the voltage, the faster the growth rate;and the longer the time, the greater the extent of the conductivepathway. The conductive pathway stops growing when the voltage isremoved. The conductive pathway shrinks, re-dissolving metal ions intothe cell body, when the voltage polarity is reversed.

FIG. 1 is a cross-section drawing showing a structure for a portion of amemory array from which many embodiments of the current invention can beconstructed. A bottom conducting line 10 overlies a substrate 8. Thesubstrate 8 may be a simple silicon wafer or it may contain up toseveral layers of integrated circuit devices and insulating layers;typically, an insulating layer intervenes between the conducting line 10of a cross-point array and a lower semiconductor layer (e.g., topportion of a silicon wafer or an epitaxial layer thereover). The bottomconducting line 10 extends from side to side in the plane of the pageand continues on past the edges of the page. For the memory array, thereare a series of conducting lines parallel to the one 10 shown lying overthe substrate 8. The bottom conducting line 10 may comprise anyconducting material suitable for integrated circuit manufacture, such asaluminum, copper, or combinations thereof. Preferably, the bottomconducting line 10 comprises tungsten and acts as a bottom electrode fordevices that will be fabricated over and in contact with the line 10. Inone arrangement, an additional layer (not shown) comprising a diffusionbarrier, preferably tungsten or tungsten nitride, is deposited over thebottom conducting line 10.

A layer of an insulating material 12 has been deposited over the bottomconducting line 10. Preferably, the insulating layer 12 has a thicknessbetween about 25 nm and 150 run, more preferably between about 35 nm and75 nm, most preferably, between about 40 nm and 60 nm. The insulatingmaterial 12 may be any insulating material that does not interactadversely with the materials used in the programmable conductor memorycell and that has enough structural integrity to support a cell formedin a via therein. Suitable materials include oxides and nitrides.Preferably, the insulating layer 12 comprises silicon nitride. Usingstandard techniques, an array of vias is patterned and etched into theinsulating layer 12. The vias are positioned so that their bottomsurfaces expose a bottom conducting line (or a diffusion barrier layerthereover). One via 14 that exposes the bottom conducting line 10 isshown in FIG. 1. The width of the via 14 is preferably between about 100nm and 180 run, more preferably between about 120 nm and 140 nm. It isin vias such as the one shown in FIG. 1 that the programmable conductormemory cells of many preferred embodiments can be constructed.

FIG. 2 shows the structure of FIG. 1 after deposition of a chalcogenideglass 16, preferably a germanium selenide (Ge—Se) glass, such as Ge₂Se₈or Ge₂₅Se₇₅, to overfill the via 14. The chalcogenide glass may bedeposited by any of a number of methods including sputtering andevaporating.

As shown in FIG. 3, the chalcogenide glass layer 16 is etched back toform a recess in the via 14, leaving only a portion 18 of chalcogenideglass remaining in the via 14. The chalcogenide glass is etched backusing an isotropic etch, such as a CF₄ dry etch or a tetramethylammonium hydroxide (TMAH) wet etch.

FIG. 4 shows the structure of FIG. 3 after doping a layer 20 of thechalcogenide glass portion 18 in the via 14 to a predetermined depth. Inone embodiment, the depth of the doped layer 20 is between about 10 nmand 20 nm. Preferably, doping comprises processing at a temperature lessthan about 340° C. and to a concentration of between about 0.1 atomic %and 1.0 atomic %. More preferably, doping comprises ion implantationwith a species such as bismuth or lead. In the illustrated embodiment,the ion implantation is performed at an energy between about 20 keV and30 keV at a dose between about 1×10¹³ atoms/cm² and 1×10¹⁴ atoms/cm².

Germanium-selenium or germanium selenide (also referred to as “Ge—Se”herein) is a p-type semiconductor. Doping germanium selenide withbismuth or lead changes the conductivity from p-type to n-type. Thus inthe structure of FIG. 4, the bottom, undoped germanium selenide portion18 and the doped layer 20 have opposite conductivity types and comprisea p-n junction diode.

In FIG. 5, another chalcogenide glass layer 22 has been deposited,overfilling the via. This layer 22 forms a programmable conductor memorycell and preferably comprises a germanium selenide glass, such as Ge₂Se₈or Ge₂₅Se₇₅, with a conductive material, such as metal ions, preferablysilver ions, mixed or dissolved therein. In one embodiment, the layer 22is formed by co-sputtering Ge—Se glass, such as from a pressed powdertarget, and silver. In other embodiments the Ge—Se glass may bedeposited first and then the silver ions diffused therein, such as byphotodissolution, as is known in the art of programmable conductormemory cell fabrication. Preferably, the concentration of silver in thechalcogenide glass memory element is between about 20 atomic % and 32atomic %, more preferably, between about 29 atomic % and 31 atomic %.The skilled artisan can, however, arrive at a desired ratio within oroutside these ranges through routine experimentation.

There are two illustrated embodiments for completing the integratedprogrammable conductor memory cell and diode device as described thusfar. One embodiment is shown in FIGS. 6A-6B. The other is shown in FIGS.7A-7C.

In FIG. 6A, the structure of FIG. 5 has been planarized, leaving aprogrammable conductor chalcogenide glass memory element 24 with metalions mixed or dissolved therein filling the recess in the via and levelwith the top surface of the insulating layer 12. A layer of a conductingmaterial, preferably from Group IB or Group IIB, more preferably,silver, has been deposited over the chalcogenide glass element 24 andthe insulating layer 12. Preferably, the thickness of the conductinglayer is between about 50 nm and 100 nm. The conducting layer has beenpatterned and etched using standard methods to form a top electrode 26for the integrated programmable conductor memory cell and diode device.In one aspect of the invention, a diffusion barrier (not shown), such astungsten nitride, is deposited over the chalcogenide glass element 24before forming the top electrode 26. A diffusion barrier may also bedeposited over the top electrode 26. Another possibility is that the topelectrode 26 is a multi-layered structure that includes a diffusionbarrier layer as one of its components.

In FIG. 6B, another conducting layer has been deposited, patterned andetched to form a top conducting line 28 extending into and out of theplane of the paper. Preferably the top conducting line 28 comprisestungsten and connects a row of integrated programmable conductor memorycell and diode devices in the memory array. Tungsten also has theadvantage of acting as a diffusion barrier for chalcogenide glassspecies.

FIG. 6B is a cross-section view of an integrated programmable conductormemory cell and diode device in a via that shows the structure of anillustrated embodiment. The device comprises a first diode element 18,having a first conductivity type, a glass electrolyte element 24 havingmetal ions, such as silver, therein over the first diode element 18 anda top electrode 26 in contact with the glass electrolyte element 24. Thestructure further comprises a second diode element 20, having a secondconductivity type, between the first diode element 18 and the glasselectrolyte element 24. In the illustrated embodiment, the diodeelements 18, 20 and the programmable conductor memory cell or glasselectrolyte element 24 all comprise a chalcogenide glass, such as Ge—Seglass. The first diode element 18 is not intentionally doped and isnaturally p-type. The second diode element 20 contains an n-type dopantsuch as bismuth or lead. Preferably there is a diffusion barrier layer(not shown) comprising titanium between the second diode element 20 andthe glass electrolyte element 24. The first diode element 18 is inelectrical contact with the bottom conducting line 10. A portion of thebottom conducting line 10 that is directly below and in electricalcontact with the first diode element 18 forms a bottom electrode for theintegrated programmable conductor memory cell and diode device.

There may also be a diffusion barrier layer (not shown) below the firstdiode element 18 and a diffusion barrier layer over the chalcogenideglass element 24. In one embodiment, the thickness of the diffusionbarrier layer is between about 10 nm and 40 nm. Materials for thediffusion barrier layers include titanium, tungsten and tungstennitride.

In the second illustrated embodiment for completing the structure ofFIG. 5, as shown in FIG. 7A, a layer of a conducting material 30,preferably from Group IB or Group IIB, more preferably silver, has beendeposited over the chalcogenide glass layer 22. Preferably, thethickness of the conducting layer is between about 50 nm and 100 nm. InFIG. 7B, both the conducting layer and the chalcogenide glass layer havebeen patterned and etched to form a programmable conductor chalcogenideglass memory element 32 with metal ions mixed or dissolved therein andan electrode 34 for the integrated programmable conductor memory celland diode device.

In FIG. 7C, another conducting layer has been deposited, patterned andetched to form a top conducting line 28 extending into and out of theplane of the page. Preferably the top conducting line 28 comprisestungsten and connects a row of integrated programmable conductor memorycell and diode devices in the memory array.

FIG. 7C is a cross-section view of an integrated programmable conductormemory cell and diode device in a via that shows the structure of anillustrated embodiment. The device comprises a first diode element 18,having a first conductivity type, a glass electrolyte element 32 havingmetal ions, such as silver, mixed or dissolved therein over the firstdiode element 18 and a top electrode 34 in contact with the glasselectrolyte element 32. The structure further comprises a second diodeelement 20, having a second conductivity type, between the first diodeelement 18 and the glass electrolyte element 32. In one embodiment, thediode elements 18, 20 and the programmable conductor memory cell orglass electrolyte element 32 all comprise a chalcogenide glass, such asGe—Se glass. The first diode element 18 is not intentionally doped, andis naturally p-type. The second diode element 20 contains an n-typedopant such as bismuth or lead. Preferably there is a diffusion barrierlayer (not shown) comprising titanium between the second diode element20 and the glass electrolyte element 24.

There may also be a diffusion barrier layer (not shown) below the firstdiode element 18 and a diffusion barrier layer over the chalcogenideglass element 32. In one embodiment, the thickness of the diffusionbarrier layer is between about 10 nm and 40 nm. Materials for thediffusion barrier layers include titanium, tungsten and tungstennitride.

In another embodiment of the current invention and with reference againto FIG. 4, the entire thickness of the chalcogenide glass portion 18 isdoped. This embodiment is shown in FIG. 8. The doped chalcogenide glasslayer 36 extends down to the bottom conducting line 10 or a diffusionbarrier layer thereover (not shown) and forms the first diode element.Hereinafter, processing proceeds much as described for the embodiment inFIGS. 5, 6A and 6B.

Another chalcogenide glass layer is deposited, overfilling the via. Thestructure is planarized, leaving the chalcogenide glass layer 38 withmetal ions therein filling the recess in the via and level with the topsurface of the insulating layer 12. This layer 38 functions both as thesecond diode element in contact with the first diode element 36 and asthe programmable conductor memory element and preferably comprises agermanium selenide glass, such as Ge₂Se₈ or Ge₂₅Se₇₅, with a conductivematerial, such as metal ions, preferably silver ions, mixed or dissolvedtherein. A layer of a conducting material, preferably from Group IB orGroup IIB, more preferably, silver, is deposited over the chalcogenideglass element 38 and the insulating layer 12. Preferably, the thicknessof the conducting layer is between about 50 nm and 100 nm. Usingstandard methods, the conducting layer is patterned and etched to form atop electrode 26 for the integrated programmable conductor memory celland diode device.

In one aspect of the invention, a diffusion barrier (not shown), such astungsten nitride, is deposited over the chalcogenide glass element 38before forming the top electrode 26. Alternatively, a diffusion barriermay be deposited over the top electrode 26. Another possibility is thatthe top electrode 26 is a multi-layered structure that includes adiffusion barrier layer as one of its components. A second conductinglayer is deposited, patterned and etched to form a top conducting line28 extending into and out of the plane of the page. Preferably the topconducting line 28 comprises tungsten and connects a row of integratedprogrammable conductor memory cell and diode devices in the memoryarray. Tungsten also has the advantage of acting as a diffusion barrierfor chalcogenide glass species.

FIG. 8 is a cross-section view of an integrated programmable conductormemory cell and diode device in a via that shows the structure of anillustrated embodiment. The integrated PCRAM (memory and diode device)36, 38 is formed in a via in an insulating layer 12, preferably siliconnitride. A conducting line 10 comprising a metal such as tungsten,extends along the bottom of the via and off the edges of the page. Theremay be first diffusion barrier layer (not shown) between the conductingline 10 and the first layer of chalcogenide glass 36.

The first layer of chalcogenide glass 36 has n-type doping from a dopantsuch as bismuth or lead. A second layer of chalcogenide glass 38,infused with silver, is in contact with the first layer of chalcogenideglass 36. In one arrangement, the chalcogenide glass is Ge₂Se₈ orGe₂₅Se₇₅. The two layers 36, 38 comprise a p-n junction, and the secondlayer 38 functions also as a programmable conductor memory element. Atop electrode layer 26 lies over the second chalcogenide glass layer 38and may comprise silver. A conducting line 28, extending into and out ofthe page is in contact with the electrode 26. In one aspect of theinvention, the conducting line 28 comprises tungsten and acts also as adiffusion barrier. In another aspect of the invention, a separatediffusion barrier layer (not shown) is used either below or above theelectrode 26. Another embodiment of the invention can be describedstarting with the structure of FIG. 1. As discussed above, a bottomconducting line 10 overlies a substrate 8. Using standard techniques, anarray of vias is patterned and etched into the insulating layer 12. Onevia 14 is shown in FIG. 1. It is in this via that the programmableconductor memory cell of this embodiment will be constructed.

With reference to FIG. 9, a layer of tungsten silicide 40 is depositedat the bottom of the via. A first diode element 42, preferablycomprising a doped polysilicon layer having a first type conductivity,is deposited over the tungsten silicide layer 40. A second diode element44, preferably comprising a doped polysilicon layer having a second typeconductivity, opposite to the first type conductivity, is deposited overthe first diode element 42. The two polysilicon layers 42, 44, havingopposite conductivity types, form a polysilicon diode.

A diffusion barrier layer 46, preferably comprising tungsten nitride, isdeposited over the second diode element 44. A chalcogenide glass element48, preferably a germanium selenide glass with metal ions, preferablysilver ions, mixed or dissolved therein, is formed by depositing theglass over the diffusion barrier layer 46 and then planarizing the glasslayer to make it level with the top surface of the insulating layer 12.A layer of a conducting material, preferably from Group IB or Group IIB,more preferably, silver, has been deposited over the chalcogenide glasselement 48 and the insulating layer 12. Preferably, the thickness of theconducting layer is between about 50 nm and 100 nm. The conducting layerhas been patterned and etched using standard methods to form a topelectrode 26 for the integrated programmable conductor memory cell andpolysilicon diode device. Preferably a diffusion barrier (not shown),more preferably, tungsten nitride, is deposited over the chalcogenideglass element 48 before forming the top electrode 26. Finally, althoughnot shown in FIG. 9, a conducting line may be provided as describedabove with reference to FIGS. 6B and 7C.

FIG. 9 is a cross-section view of an integrated programmable conductormemory cell and diode device that shows the structure of an illustratedembodiment. The first polysilicon layer 42, having a first conductivitytype doping, lies in a via in an insulating layer 12. There is a secondpolysilicon layer 44, having a second conductivity type doping, oppositeto the first conductivity type, between the first polysilicon layer 42and a diffusion barrier layer 46. For example, the first polysiliconlayer 42 may have p-type doping, and the second polysilicon layer 44 mayhave n-type doping. There is a layer of germanium selenide glass 48,containing metal ions, over the diffusion barrier layer 46. There is atop electrode 26 over the germanium selenide glass 48. The top electrode26 may comprise both a conducting layer and a diffusion barrier layer.

Another aspect of the invention can be described with reference to FIG.10. A silicon substrate 8 is shown with a region 52 doped to have afirst type conductivity, preferaby p⁺. The region 52 forms the firstdiode element.

A layer of an insulating material 12 has been deposited over thesubstrate 8. Preferably the insulating layer 12 has a thickness betweenabout 50 nm and 150 nm, more preferably between about 95 nm and 105 nm.The insulating material 12 may be any insulating material that does notinteract adversely with the materials used in the programmable conductormemory cell or in the diode and that has enough structural integrity tosupport a cell formed in a via therein. Suitable materials includeoxides and nitrides. Preferably the insulating layer 12 comprisessilicon nitride. Using standard techniques, an array of vias ispatterned and etched into the insulating layer 12. Two such vias,containing integrated programmable conductor memory cell and diodedevices are shown in FIG. 10.

A polysilicon layer 54, having a second conductivity type, preferablyn⁺, opposite to the first conductivity type of the doped region 52, isdeposited into the via in contact with the doped region 52 of thesubstrate 8. Polysilicon layer 54 forms the second diode elements and,together with doped region 52, forms p-n junction diodes.

Diffusion barrier layers 56, preferably comprising tungsten nitride, aredeposited over the second diode elements 54. Chalcogenide glass elements58, preferably germanium selenide glass with metal ions, preferablysilver ions, mixed or dissolved therein, are formed by depositing theglass over the diffusion barrier layers 56 and then planarizing theglass to make it level with the top surface of the insulating layer 12.A layer of a conducting material, preferably from Group IB or Group IIB,more preferably, silver, is deposited over the chalcogenide glasselements 58 and the insulating layer 12. Preferably, the thickness ofthe conducting layer is between about 50 nm and 100 nm. The conductinglayer is patterned and etched using standard methods to form topelectrodes 26 for the integrated programmable conductor memory cell andpolysilicon diode devices 58, 52, 54. Preferably a diffusion barrier(not shown), more preferably, tungsten nitride, is deposited over thechalcogenide glass elements 58 before forming the top electrodes 26.

A conducting line 28, extending into and out of the page, is in contactwith the electrode 26. A conductive plug 60, preferably comprisingpolysilicon or a metal such as tungsten, makes contact to the dopedsilicon substrate region 52 and to conducting line 62, thus providingelectrical connections for the integrated programmable conductor memorycell and diode device of FIG. 10. Conducting line 62 is insulated fromconducting line 28 by layer 64, preferably comprising BPSG(borophosphosilicate glass).

Another aspect of the invention can be described with reference to FIG.11. A silicon substrate 8 is shown with a region 52 doped to have afirst conductivity type, preferably p⁺. The region 52 forms the firstdiode elements for integrated programmable conductor memory cell anddiode devices.

A layer of polysilicon with conductivity, preferably n⁺, opposite to theconductivity of the doped region 52 of the substrate 8 is deposited. Thepolysilicon layer is patterned and etched to form the second diodeelements 54. Preferably, a diffusion barrier layer, such as tungsten,tungsten nitride or titanium, is deposited onto the polysilicon layerand then patterned and etched with the polysilicon layer, thus formingdiffusion barrier layers 56 over the second diode elements 54.

A layer of material 64, preferably silicon nitride, is depositedconformally onto the second diode elements 54 and diffusion barrierlayers 56 to act as an etch stop for a subsequent chemical-mechanicalplanarization step. An insulating layer 66, preferably comprisingsilicon oxide formed from TEOS, is deposited to a thickness that atleast covers the top surface of layer 64. Chemical-mechanicalplanarization is performed until the top portions of layer 64 areexposed to make a flat top surface for silicon oxide layer 66. Theexposed portions of layer 64 are patterned and etched to expose at leasta portion of a top surface of the diffusion barrier layer 56.

A layer of insulating material 12, preferably silicon nitride, isdeposited over the silicon oxide layer 66. The layer 12 is patterned andetched to form vias down through layer 64 and onto diffusion barrierlayer 56. A chalcogenide glass layer is deposited, overfilling the vias.The chalcogenide glass forms the programmable conductor memory cells 58and preferably comprises a germanium selenide glass, such as Ge₂Se₈ orGe₂₅Se₇₅, with a conductive material, such as metal ions, preferablysilver ions, mixed or dissolved therein. In one embodiment, the glass isformed by co-sputtering Ge—Se glass, such as from a pressed powdertarget, and silver. In other embodiments the Ge—Se glass may bedeposited first and then the silver ions diffused therein, such as byphotodissolution, as is known in the art of programmable conductormemory cell fabrication. Preferably, the concentration of silver in thechalcogenide glass memory element is between about 20 atomic % and 36atomic %, more preferably, between about 29 atomic % and 32 atomic %.

A layer of a conducting material 27, preferably from Group IB or GroupIIB, more preferably silver, is deposited over the chalcogenide glasslayer 58. Preferably, the thickness of the conducting layer is betweenabout 50 nm and 100 nm. Both the conducting layer 27 and thechalcogenide glass layer 58 are patterned and etched to formprogrammable conductor chalcogenide glass memory elements 58 with metalions mixed or dissolved therein and electrodes and conducting lines 27for the memory cells 58.

A layer of insulating material 64, preferably comprising BPSG(borophosphosilicate glass), is deposited over the conducting lines 27and planarized. A via is etched through insulating layers 64, 12 and 66,down to expose a portion of the doped region 52 of the substrate 8. Thevia is filled with conducting material, preferably polysilicon or ametal such as tungsten, thus forming a conductive plug 60 that makescontact to the doped silicon substrate region 52. A conductive line,preferably comprising aluminum or copper, is formed over the BPSG 64 andmakes contact with the conductive plug 60, and thus to the diodes in theintegrated programmable conductor memory cell and diode devices.

This invention has been described herein in considerable detail toprovide those skilled in the art with the information needed to applythe novel principles and to construct and use such specializedcomponents as are required. However, it is to be understood that theinvention can be carried out by specifically different equipment anddevices, and that various modifications, both as to the structure and asto the method of fabricating the structure, can be accomplished withoutdeparting from the scope of the invention itself.

1-60. (canceled)
 61. A method for making a PCRAM cell with an integratedthin film diode in a via, comprising: providing a diffusion barriermaterial at a bottom of the via; depositing a first chalcogenide glassto fill the via; etching the first chalcogenide glass back to form arecess in the via; doping the first chalcogenide glass to apredetermined depth after etching; forming a mixture of a secondchalcogenide glass and a first conductive material to fill the via afterdoping; and depositing a second conductive material over the mixture.62. The method of claim 61, wherein the first chalcogenide glass and thesecond chalcogenide glass each comprise germanium (Ge) and selenium(Se).
 63. The method of claim 62, wherein the first chalcogenide glassand the second chalcogenide glass comprise Ge₂Se₈ or Ge₂₅Se₇₅.
 64. Themethod of claim 61, wherein the first chalcogenide glass is deposited bysputtering.
 65. The method of claim 61, wherein the first chalcogenideglass is deposited by evaporating.
 66. The method of claim 61, whereinetching the first chalcogenide glass back comprises an isotropic etch.67. The method of claim 66, wherein the isotropic etch comprises a CF₄dry etch.
 68. The method of claim 66, wherein the isotropic etch is anaqueous base.
 69. The method of claim 66, wherein the isotropic etchcomprises tetramethyl ammonium hydroxide (TMAH).
 70. The method of claim66, wherein the isotropic etch comprised ammonium hydroxide.
 71. Themethod of claim 61, wherein doping the first chalcogenide glasscomprises processing at a temperature less than about 340° C.
 72. Themethod of claim 71, wherein doping the first chalcogenide glasscomprises ion implantation.
 73. The method of claim 72, wherein ionimplantation comprises a species selected from the group consisting ofbismuth and lead.
 74. The method of claim 73, wherein ion implantationis performed at an energy between about 20 keV and 30 keV at a dosebetween about 1×10¹³ atoms/cm² and 1×10¹⁴ atoms/cm².
 75. The method ofclaim 71, wherein doping the first chalcogenide glass to a predetermineddepth comprises doping to a depth of between about 10 nm and 20 nm,thereby forming a p-n junction with the underlying chalcogenide glass.76. The method of claim 71, wherein doping the first chalcogenide glassto a predetermined depth comprises doping through the entire depth ofthe chalcogenide glass, thereby forming a p-n junction at the boundaryof the first, doped chalcogenide glass and the mixture of the secondchalcogenide glass and the first conductive material.
 77. The method ofclaim 61, wherein forming the mixture of the second chalcogenide glassand the first conductive material comprises co-sputtering germaniumselenide from a pressed powder target and silver from a silver target.78. The method of claim 61, wherein depositing the second conductivematerial over the mixture of the second chalcogenide glass and the firstconductive material comprises depositing a layer of second conductivematerial selected from the group consisting of Group IB or Group IIBmetals to a thickness of about 50 nm to about 100 nm.
 79. The method ofclaim 78, wherein both the first conductive material and the secondconductive material comprise silver.
 80. The method of claim 79, furthercomprising patterning the silver layer to form a top electrode for thePCRAM cell.
 81. The method of claim 80, further comprising providingconducting lines, in contact with the top electrode for the PCRAM celland providing connections to other PCRAM cells.
 82. The method of claim81, wherein the conducting lines comprise tungsten.
 83. A method offabricating a programmable conductor memory device wherein each memorycell has an ancillary diode, comprising: etching a via in a siliconnitride layer over a tungsten region; filling the via with germaniumselenide (Ge—Se); etching back the Ge—Se to form a recess in the via;ion implanting the Ge—Se with bismuth; co-sputtering a mixture of Ge—Seand silver (Ag) depositing and patterning a silver layer onto themixture of Ge—Se and Ag to form a top electrode; and depositing a topconducting layer of tungsten.
 84. A method of forming a memory cell,comprising: providing a polysilicon diode; forming a diffusion barrierlayer over the diode; depositing germanium selenide glass over thediffusion barrier; and infusing the germanium selenide glass with metalions.